The present invention generally relates to semiconductor device manufacturing, and particularly to polishing an individual die within a semiconductor wafer.
Rapid progress in semiconductor device integration demands smaller wiring patterns or interconnections connecting active areas. As a result, the tolerances regarding the planarity or flatness of the semiconductor wafers are also becoming smaller. One way of flattening the surface of a semiconductor wafers is to polish the wafer.
In general, a semiconductor wafer can be polished to provide a planarized surface to remove surface variations or defects. A polishing process often used is a chemical mechanical polishing (“CMP”) and may be utilized to improve the quality and reliability of semiconductor devices. The CMP process may be performed during the formation of various devices and integrated circuits on the wafer.
The CMP process involves holding a thin flat wafer of semiconductor material against a rotating polishing pad under a controlled downward pressure and the wafer is above the polishing pad. A polishing slurry such as a solution of alumina or silica may be utilized as an abrasive medium. A rotating polishing head or wafer carrier is typically utilized to hold the wafer under controlled pressure against a rotating polishing pad. The polishing pad is typically covered with a relatively soft wetted pad material such as blown polyurethane.